- Featured in:
-
More Asic Design Engineer Resumes
Use these Asic Design Engineer samples as a guideline or visit our extensive library of customizable professional resume templates.
Select
Customize
Download
Find out what is the best resume for you in our Ultimate Resume Format Guide.
Additional Engineering Resume Samples
Asic Design Engineer Resume Samples
No results found
0-5 years of experience
Design, verification, and FPGA support for development of NAND flash controllers.
- Built and implemented more flexible and automated models, reducing design analysis time by 50%
- Led and facilitated 5 member verification team to develop the team’s ability to examine work Design, verification, and FPGA support for development of USB keys, SD cards, and SSD drives.
- Developed more efficient checkers and monitors, and led 5-member verification team to complete validation of all projects 25% ahead of schedule.
- Authored and updated datasheets and application notes for improved customer support.
- Collaborated closely with firmware and software teams to prioritize debugging efforts and feature implementation.
0-5 years of experience
Re-designed existing architectural simulation tool’s checker module using C++ and gem5.
- Modeled Load/Store Unit of future processor’s performance model using micro-architectural specification documents, C++, Python, and gem5.
- Ran EEMBC, SPEC2K/SPEC2K6, Stream, Linpack Benchmark workloads on CPU simulation model. Compared and analyzed scores with existing and competing CPU’s.
- Identified micro-architectural performance bottleneck in Load/Store Unit which led to ~5% improvement in benchmark score of future CPU design.
- Created framework, workloads for running JavaScript benchmarks V8/Octane and SunSpider using GNU cross compilers, Simpoint tool, and gem5.
- Ran full chip verification tests and resolved ARM v7/v8 architectural bugs in RTL designs.
- Took ownership of identification and exploration of promising new academic researches in Computer Architecture.
0-5 years of experience
Member of the ASIC design team that was responsible for all aspects of architecture, design, and debug of high speed switch fabric ASIC for next generation Avici Core Router. The ASIC consisted of the following: SPI-4.2 system interface for insertion/extraction, PCI Bus Target core for the processor maintenance bus, internal crossbar switch, and high speed fabric in/out links.
- Developed architecture, wrote hardware specifications, designed and debugged Verilog modules for the following: 8×8 crossbar data arbiter, in-system Memory BIST, and internal proprietary processor maintenance bus that interfaces to the PCI Bus Target core and to all of the ASIC’s internal functional modules.
- Completed design tasks successfully 1 month ahead of schedule and under budget.
- Volunteered to help in the following areas: writing Python scripts that generate Verilog RTL code, functional verification, and in-system Memory BIST and BISR.
- Saved development time and money by writing Python scripts that generated Verilog code for all the ASIC internal registers and memories.
- Wrote and debugged VERA test benches and tests.
6-10 years of experience
Designed and simulated 3D Graphics functions in a Graphics Rasterization ASIC and Integrated Graphics Memory Controller ASIC. Modules including Texture Mapping; specialized Cache Controller for pixel and texel data; Address Generation logic; Specialized Cache Controller for pixel data.
- Achieved 100% functionality in the first pass: (1) Combined two ASICs in one dual mode Memory Controller / Peripheral Interface chip. (2) Adding new customer features to an existing Video Pixel Memory Interface chip design.
- Designed and simulated functions for a 2D Graphics Rasterizer ASIC including Direct Framebuffer Support, Blockwrites, Left/Right clipping of BLTs, Performed Timing.
- Designed a Microchannel Bus modem communications adapter PCB board.
0-5 years of experience
Responsible for developing golden model, logic design, test bench, extracting layout parameters, pre/post layout verifications, timing analysis(Hspice) and backend support of 0.6u, double metal, 64-bit cascadable Single nibble error correction, Double nibble error detection (S4EC-D4ED) custom chip using Fujiwara block codes. Developed power bus scheme, clock trees and drivers. A thorough critical path, switching and electro-migration analyses were done using 256 pin BGA parameters and Hspice. Device worked to all specifications first time.
- Redesigned and verified 0.6u, 64-bit cascadable Single error correction, Double error detection (SEC_DED) chip using modified Hamming block codes.
- Redesigned 15 double density and octal family products to faster, smaller geometry arrays and new processes. Devices included FCT, LVCMOS, High, Balanced, BD-Lite and CMOS drive types.
- Designed pre-scalar, post-scalar dividers and control logic for PLL devices.
0-5 years of experience
Designed and fully characterized a time-interleaved SAR ADC AFE (track and hold/buffer) in IBM 32nm SOI
- Helped design and fully characterize two 5 GHz SERDES transmitters in IBM 45nm SOI
- Additional tapeouts (resimulated with updated PDK, verify functionality): A frequency doubler in IBM 5PAx (2.5-5 GHz and 5-10 GHz), a 3x coupled VCO and a LNA design in IBM 9HP
- Assembled and assisted in bring-up of an ultra-high speed ADC slice testing platform
0-5 years of experience
Worked in a start-up environment with multiple responsibilities to develop proprietary networking processors.
- Responsible for chip floor-plan, and pad-ring design.
- Compiled instruction set and integrated of a Tensilica programmable microprocessor into the product.
- Performed RTL design, constraint development, logic synthesis DC/DFT, and timing analysis/debug.
- Developed chip-level verification environment, wrote test-bench, performed RTL integration, adapted vendors IP test suites.
- Performed FPGA logic synthesis to build prototype for system and functional verifications prior to tape-out.
0-5 years of experience
Held responsibility for ARM925 v2, v2.5, and v3. Designed memory management unit using Contest-Addressable Memory.
- Designed System Bus. Performed synthesis and STA.
- Oversaw cache and buffer systems verification, using top-level ARM assembly tests as well as RTL test benches.
- Contributed to CMOS IO pad cell library development and DSP core design. Designed and developed CMOS 0.35u to 0.25u standard cell and IO pad cell library, including layout, DRC, LVS, and HSPICE simulation.
- Oversaw RTL design and verification in model technology and Synopsys EDA environments. Contributed to RAD DSP core RTL design. Managed four-port memory simulation and verification. Performed test-bench development and verification of existing VHDL RTL designs.
- Coordinated design, simulation, and delivery of multiple sets of IO pads for TSMC, Chartered, and Burr-Brown.
0-5 years of experience
Designed part of MFP Image processing ASIC (XIPCHIP) implemented in IBM technology (~400K gates) consisting of an embedded PowerPC core, DMA subsystem, various memory and dedicated hardware interfaces, compression/decompression and image processing logic, etc.
- Participated in design verification of above ASIC in various test bench environments using PowerPC Assembler/C code at chip level and stripped down test benches at unit level.
- Implemented test logic for above ASIC as part of XILINX FPGA (runs on PCI card in LINUX PC) and worked on LINUX device driver for this card.
- Performed hardware verification of certain interfaces on follow-on MFP ASIC.
0-5 years of experience
Contributed to complex simulation for the F-135 Joint Strike Fighter program applying FPGA expertise
- Developed IO module in the testbench and modified various different levels in the hierarchy by using HDL designer
- Performed register transfer level (RTL) and gate level simulations by using ModelSim
- Completed leadership training that involved, negotiation, innovation and ACE (Achieving Competitive Excellence)
0-5 years of experience
Built and maintained Makefile flow for scan insertion, ATPG, MBIST, boundary scan, and simulation using TCL
- Worked with cross-functional teams that included PD, IP, power, and CAD
- Consistently achieved high test pattern quality and coverage (95%+) through shadow logic and test point insertion
- Created fossil repository for version control of file and script management
- Taped out six chips in the span of two years on short 12 week deadlines as well as long 60+ week deadlines
0-5 years of experience
- Technical lead for Consumer Printer Development’s first FPGA system utilizing both FPGAs and Field Programmable Interconnect technology.
- Introduced a new, innovative design verification methodology that has continued to evolve until today.
- Enabled the interconnection of 3 FPGAs, an ARM Processor and a Main Memory module.
- Increased efficiency by allowing early FW development and problem identification.
- Designed a TDM (Time Division Multiplexing) based ADC controller capable of simultaneously controlling multiple subsystems. Agile design enabled reuse in future inkjet products. Still in use today.
- Designed a DC motor controller utilizing a proprietary analog encoder scheme and integrated with the TDM ADC controller.
0-5 years of experience
- Performed VHDL design, verification, synthesis of various modules in C4-VC4 mapper ASIC for SDH applications
- Completed VHDL, functional verification and synthesis of adders, UART, multipliers in Host Terminal Protocol Controller in Xilinx XC4000.
- Developed working understanding of SONET/SDH
0-5 years of experience
Developed synthesizable and behavioral RTL codes for various modules including GPIO, SDIO, Temperature monitor, system control, clock generation and PLL blocks
- Designed, simulated and synthesized IO pads and PLL blocks in a mixed signal environment
- Implemented low-power design techniques such as clock-gating, power-gating, voltage and frequency scaling and FSM state encoding
- Defined constraints for Synopsys DC, primetime and Mentor’s 0-in
- Generated UPF files to run power aware simulation
- Verified Clock Domain Crossings
- Embedded OVL assertions and performed lint checks
- Performed functional verification at IP/SOC level
Rate This Article
[Asic Design Engineer]
Last edited by: Gabriela Barcenas, CPRW, Content Writer II -
Gabriela Barcenas
CPRW, Content Writer IIGabriela is a Certified Professional Resume Writer (CPRW) and career adviser. With 10 years of digital media experience and five years of resume writing expertise, her publication history includes fashion, education, travel, social justice, equitable design and career advice.
