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0-5 years of experience
Responsible for mechanical design and simulation of tunable semiconductor laser packages.
- Conducted GD&T exercises and improved end-to-end yield by 33%.
- Developed design concepts and supervised draftsmen in creation of 3D models, 2D detailed drawings and quality documents. Formulated and supervised execution of design verification and validation plans per industry standards.
- Standardized the design by incorporating piece-parts common to different products, enabling sourcing/procurement to negotiate lower prices with suppliers.
- Conducted rigorous FEA analysis and improved the opto-mechanical reliability of the products to eliminate future field returns.
- Improved yield of solder-attach process by 20% using DOE and statistical analysis.
10+ years of experience
Designed timing driven layout of telecommunications integrated circuits with emphasis on timing closure. Performed place and route of digital IC’s and large super blocks using state of the art CAD tools. Analyzed power and voltage drop results of chip designs.
- Completed physical design layout of network processors, network switches, and telecommunication chips on or ahead of schedule with 100% accuracy.
- Simultaneously worked across different departments within the company to meet customer needs and deadlines.
- Place and route of a very complex timing control circuit with over 100 system clocks critical to chip performance and developed strategies to ensure design met timing constraints and correlated with engineering specifications.
- Developed and administered internal web pages documenting flows, checklists and status for designs making important documentation readily accessible.
- Verified design layout using numerous CAD tools and design specifications to prevent chip failure.
- Interviewed, trained and mentored new employees, in all aspects of physical design and verification.
- Checked work of peers using detailed checklists insuring 100% accuracy.
6-10 years of experience
- Designed high performance cores that are replicated for use in next generation GPUs
- Implemented innovative low power techniques that reduced chip cooling cost by $5M
- Coordinated with RTL and Package teams to set and meet aggressive area targets that saved approx $12M in production cost compared to previous generation products.
- Enhanced the design flow to improve its runtime from 12 to 8 hours, resulting in the reduction of the project timeline by 2 weeks.
- Helped grow the team by interviewing, selecting and mentoring candidates. Assessed their skills and worked with management to develop task and growth plans.
0-5 years of experience
Lead the testing group for ADSL technology project.
- Designed a state of the art power board that allowed multiple connections for various adapters.
- Redesigned circuit board for 4ESS frame that reduced cost of manufacturing by 15%.
- QOS control with factory to ensure standards were met for any circuitry changes.
0-5 years of experience
Designed, edited, and enhanced custom high power integrated packages ranging from various BGA styles to Flip-Chip designs
- Designed in both Windows and UNIX environments
- Created drawings in MicroStation and Avanti design tools, and capture
- Maintained files electronically and administer sister sites drawing file management
- Assisted in the reworking design procedures and practices
- Served as liaison in the creation of specialized CAD tools for place and route tools
- Converted Unigraphic designs to MicroStation while tasked with assisting sister site with enhancing dual in-line product line
- Successfully Co-designed a custom package on a joint company design utilizing two different design tools, ideology, CAD tools, and processes
0-5 years of experience
Design and development of Low Power SOC chips used in Cellular and Handheld applications.
- Performed Physical Integration of large blocks ranging from 1M to 3M instances.
- Designed and developed blocks from RTL to GDSII using a timing closure flow. The tasks include floorplanning of single and multiple power domain designs, place and route, CTS, sign-off physical verification
- Evaluated and benchmarked study for area/timing/routability impact using 7 and 9 tracks library at 28nm process
- Evaluated and benchmarked study for area savings using different metal stack configurations and 9 track library.
- Enhanced methodology and APR flow for SOC physical design to improve productivity and QOR. Published the flow
0-5 years of experience
Developed and distributed the design flow for power analysis on a low power IC device.
- Performed cost saving tests using various metallization options on a high speed I.C. device.
- Interfaced with IP hardware vendors giving feedback for improvements on IP bocks.
- Documented design flows and checklists for future use by engineering teams.
- Designed power grids to power specifications of 3rd party custom digital blocks.
0-5 years of experience
- Thermally tested the effectiveness of air blocking plates and front blanks used inside LTE cabinets and created a matrix to determine the need for them.
- Designed and created a multifunctional GPS splitter bracket used in LTE cabinets.
- Modified a cabinet in Pro/E to reduce the cost by $100 per cabinet while meeting all the requirements.
- Designed multiple sheet metal parts to be incorporated into a new LTE cabinet which includes a fiber tray, mounting bracket, cable entry plate, and a I/O hatch plate.
0-5 years of experience
Utilized various place and route and verification tools to develop timing driven CDMA Technology Integrated Circuit Designs used in the cell phone industry.
- Performed Auto place and route on entire IC design using EDA Design Tools.
- Verified Integrated Circuit designs using IC verification tools.
- Modified IC Physical Design Flow to ensure designs could be routed with minimal errors.
- Verified Modem blocks of Raptor2 Chip using IC verification tools.
0-5 years of experience
Contributed to the successful tape-outs of 28nm, 40nm and 180nm technology nodes
- Designed optimal floorplans enabling a smooth work flow for the rest of the project
- Took blocks through placement, clock tree synthesis, and routing
- Closed timing for block and chip level
- Implemented physical verification for blocks and DRC for chip
- Analyzed and applied low power techniques using switch cells
- Executed physical and logical ECO for block and chip level
- Wrote Perl/Tcl scripts for common tasks to improve work efficiency
- Managed 2 interns
0-5 years of experience
Created, updated and maintained schematic documentation for Backplane/Unit/Frame designs utilizing Mentor Graphics, and other computer aided tools.
- Provided front-end support for the backplane interconnection processes and the wiring verification processes.
- Maintained the Quality Report database for ISO certification
- Provide support to the Backplane/Unit/Frame Design Teams
- Administrator for loading all documentation onto the Corporate Information Management System.
10+ years of experience
Performed planning, layout and verification of various high speed projects including AFE, DAC, ADC, ESD, analog and digital switch arrays, ultra-low current heart monitor, and test chips. Member of Layout Steering Group and new Calibre Clinic Team.
- Completed physical design of a 16×16 crosspoint switch from schematic to tape-out using a Bi-CMOS process. Collaborated regularly and closely with designer to incorporate needed changes. As a result, first pass met all specifications.
- Part of a layout team using 28nm process collaborating to build a continuous time delta-sigma modulator clocked at 8-10GHz. Completed sub-cells within the flash shuffler; biases, reference generator, calibration comparator.
- Worked with a CAD engineer to implement and support a customized roll-out of Calibre, a new tool for ADI, to default to the needed DFM rule subsets.
- Volunteered to join the newly founded Calibre Clinic Team. The Calibre Clinic Team was formed by the CAD group to provide a company wide support team, consisting of a core group of layout specialists responsible for training and supporting end users company wide.
0-5 years of experience
Design the layout for DDR3 & DDR4 memory chips technology. Read and interpret schematics to design analog and digital layout circuits. Able to troubleshoot circuits across different hierarchies of the chip.
- Validate and troubleshoot the circuitry functionality by running layout versus schematic and design rule check verifications in accordance with the fabrication procedures.
- Maintain constant communication with project lead, team members and partner about assignment updates and inquiries related to project specifications.
- Create sub-circuits and verify their logical functionalities using hspice, CosmoScope and Under Toe.
- Works on full chip floor planning and box estimations.
- Compose sub-blocks PRCs schematic to determine metal lengths in layout.
6-10 years of experience
Led the effort to conduct a performance analysis of different vendor library flavors and influenced a purchasing decision made by management.
- RLS-DA for XScale StrongARM CPU team. Installed, developed, presented, drove the deployment and constantly supported design tools, libraries, environments and flows to perform synthesis, APR and timing convergence on design blocks.
- Collaborated with External Product Applications engineers and coordinated working groups to facilitate flow development that resulted in speedy resolution of issues and the successful implementation of several processor projects, balancing performance with schedule.
- Successfully owned and completed design blocks for post-layout timing convergence over multiple projects. Owned post-layout convergence activities of units across various Xscale projects balancing quality with schedule. The activities include performance verification, allit run, reliability verification, formal verification, noise analysis, layout edits in APR tool, electrical rules checking, interfacing with mask design team, final quality reviews and promotion of the fub.
- Drove the development of the RC correlation flow used to correlate PC’s steiner-route estimated nets vs post-route extracted nets based on PC’s recommended methodology for RC correlation. Constantly coordinated and communicated across cross functional teams to drive flow related dependencies.
- Worked on development and deployment of a scan insertion flow when dealing with EBB’s to provide a more automated and accurate scan insertion approach for internal scan using the EDT blocks. Worked with the Synopsys Tech AEs’ to develop a new scan insertion approach using “ctlgen models” which aided in the specification and incorporation of chain length and chain elements for custom EBBs’ within existing scan chains during the scan stitching process. This was successfully used by implementation owners to perform scan insertion. Also developed and deployed hardware units used to increase the scannability and testability of Intel chipsets.
- Experience in initiating and driving the creativity of a cross-functional team to facilitate the resolution of complex technical issues and to balance quality with schedule.
- Experience in obtaining customer feedback through test group assessment which improved existing flows and methodologies and productivity.
- Good verbal / written communication skills demonstrated by numerous presentations to management, senior colleagues as well as peers.
- Certified in Dale Carnegie’s Course for Building Interpersonal Communication Skills.
0-5 years of experience
Projects: Graphics – Ivybridge (22 nm), Broadwell (14 nm), Low Power 14 nm, 10 nm SoCs
- Successfully owned and accomplished design synthesis, static timing analysis, floor planning, relative placement of RPs, clock drop-off points planning, APR flow execution (including post CTS/Route) and DRC convergence on SRAM L3 cache, L3 node, digital sampler and various graphics rendering design blocks (block size up to 2.0 Million gates) on core chip designs.
- Section Timing Owner, rolled up section netlists, managed PV execution and issues, drove timing fixes involving repeater flops insertion, duplication and RTL fixes along with RTL design team for L3 design partitions.
- Drove the RTL design change notification (DCN) in splitting designs and presented analytic data to senior engineers, for SRAM L3 cache design to improve throughput, which saved more than 2 months of design cycle time.
- Achieved timely convergence of complex designs by building RTL models from validation area and integrating them, before official model release.
- Implemented power stitching for SoC SRAM voltage domain, in multi-voltage low power design.
- Owned section quality and managed issue resolution related to RTL and structural design flow rules.
- Performed critical Engineering Change Orders (ECOs), setup/hold conflict timing paths fixes, quality fixes and clock point connections assisting RTL team for various partitions.
- Supported designs from RLS till Layout Tape-Out with all the successful quality checks and several audits.
- Developed automation scripts for extracting analytic data, metal utilization calculation, swapping slower to faster cells from performance verification reports, gate to gate formal verification and fast scan check.
- Mentored interns, new engineers on ECOs, physical design flows and in developing timing and routing data collection scripts.
0-5 years of experience
- Contributed in a global team environment serving both internal and external customers
- Performed physical design tasks on digital and mixed-signal cores using IBM EDA tools
- Designed with IBM cu08 (90nm), cu65hp (65nm), and cu45hp (45nm) ASIC design systems
- Followed IBM ASIC Design Methodology for floor planning, placement, routing, power routing, clock tree synthesis, static timing closure, and IR drop analysis
- Generated physical rules including CDL, GDS, LEF, NSE TCL, noise abstract
- Performed methodology checks, design rules checks (DRC) using Calibre, and layout and verification specification (LVS) checks using Hercules
- Completed physical design process, closed timing, generated and checked rules for ARM Embedded Trace Module (ETM) R4 in cu08 design system and multiple iterations of Chip-to-Chip calibration core (C2CPHYCAL) in cu65hp design system
0-5 years of experience
Worked in a team tasked with developing several microprocessor support chips for use in a Symmetric Multiprocessing RISC based computer.
- Produced the physical designs for four large chips utilizing random logic and structured datapath elements.
- Mastered all back-end design tools including but not limited to floor-planning, place & route, LVS, DRC, static timing, clock-tree balancing, power grid analysis and layout, extraction, and signal integrity.
- Worked as a circuit design engineer for approximately six months developing a high speed incrementor from concept to fully verified layout.
0-5 years of experience
- Designed layout plans in AutoCAD for substations in Birmingham, Eastern and Mobile Divisions
- Coordinated with construction crews, environmental and other design engineers on capital projects
- Supervised storm teams during the restoration of distribution systems during storm duty
0-5 years of experience
Responsible for ASIC physical design tasks including routing, clock-tree insertion, antenna removal, timing closure, power analysis, crosstalk analysis, layout LVS/DRC, and release to manufacturing. Projects included:
- Physical layout services for customer’s switch chipset. Chipset consisted of three ASICs working together.
- Formal verification of customer RTL code versus netlist.
- Design a development/demo ASIC to showcase LSI Logic’s ARM, GigaBlaze, RapidChip, and DDR technologies. Tasks included design/RTL-coding of Serial-Management Interface, AMBA bus interface, and circuitry to utilize LSI Logic’s GigaBlaze high-speed SERDES. Also performed synthesis, simulation, and timing closure at system-level.
0-5 years of experience
Mechanical system level design and documentation of racks and cabinets
- CREO 2/Pro Engineer and AutoCad used in integrating telecommunication equipment in racks and cabinets.
- Project management.
- Plan and analyze incoming projects.
- Perform additional assignments and duties as directed and as business necessitates.
- Developed the product models, drawings, and documentation.
0-5 years of experience
- Coordinated with other design teams to achieve efficient process for development of ASIC library
- Floor Planning at Full chip level for DSP devices. Layout integration into standard ASIC library
- Characterized newly designed and existing cells for specific application using Autochar software
0-5 years of experience
Macro Team Lead Designer GPUL and GP
- Primary responsibilities included Random logic macro synthesis and build process, physical design of (35) random logic macros for pervasive function (RAS and I/O), random logic macro place and route, random logic macro timing analysis and design verification, design ground rules, methodology and layout versus schematic checking,
- Interfaced with software tool developers to define new design tools and implemented enhancements to existing tools
- IDU Lead Integrator GQ, GR
- Primary responsibilities included meeting physical design requirements of the IDU for GQ, GR, Achieving optimum unit floorplan that met unit level timing and noise results using 3DX extraction, coordinated unit I/O pin assignment with core and unit integrators, interfaced with core integrator to negotiate metal blockage/contract requirements for unit routing, generated powerbus distribution and unit clock pins, unit routing, via generation and layout for unit and PD build process of 18 macros used in unit, successfully completed and processed all required unit and RLM DRC/LVS checking jobs to achieve clean GPA audit and continually maintained timely turnaround of unit level changes.
- Effectively interfaced with circuit designers to verify macro layouts were compliant with the PD requirements and guidelines for PIN accessibility and POWER periodicity, worked with the PD software developers to BETA test new code and made recommendations for updates and improvements.
- IDU and LSU Integrator GS
- Responsibilities included meeting physical design requirements of IDU and LSU units for GS. Unit level integration, unit level floorplanning, powerbus design, unit I/O assignment, place and route, timing closure, clock tree generation, physical verification, 3D extraction, DRC and LVS, developed PERL scripts for PD build of 20 macros and other applications
- Mentored and trained new team members on the design tools flow, PD process and methodology flow, worked with other teams to improve design automation tools and methodologies.
0-5 years of experience
- Owned 4 blocks across 2 GPU chips, each chip as large as 18x18mm and running at nearly 900 MHz.
- Approached a wide variety of timing problems with both automatic scripted fixes and custom manual
- Evaluated specific floorplans involving RAM placements, density screening, module zoning, placement
- Worked closely with the frontend designer to resolve timing violations that could not be fixed with physical ECOs.
- Ran IR drop analysis for power awareness, and determined the IR drop gradient of power bumps.
0-5 years of experience
Environmental Monitoring and Control chips physical design and tapeout 8-12 chips/year.
- Created low power ring and mash placement scripts. Digital blocks P&R.
- Setup AMS environment, design automation using Skill code and Perl scripts.
- Tested and compared TSMC and Chartered 90nm-45nm LVS and DRC rules.
0-5 years of experience
Top level floor planning, layout, and full chip verification of 10Gb/s (OC192) transceivers designed to address future systems of 40Gb/s (OC-768), using TSMC .13um technology. Circuits included: VCOs, VCOBuffers, Demuxes, Voltage Regulators, DACs, Loopfilters, Ring Oscillators, Bias Blocks, ESD Structures, standard cell libraries, and other various high speed digital blocks.
- Handled and implemented standard design kit elements. Elements included: interdigitated metal capacitors, inductors, varactors and transmission lines. Mentor Graphics rule deck development using Skill code language.
- Proficient Cadence and Mentor Graphics tool experience. Familiar with IBM, Lucent and TSMC foundry procedures; .5, .35, .18, .15, .13, .09um (Lucent/TSMC), 7SF, 7HP, 6HP, .18, .13um RF CMOS and LVOD.
- Experienced in matching, electron migration, symmetry, power busing, balancing of critical signals and IR drop.
0-5 years of experience
Worked with IBM Methodology for ASIC designs using 32nm
- Use floorplanner for hard macros and re-arrange soft-macros for optimum design minimizing congestion and timing
- Build and modify clock network to reduce skew and Insertion delays
- Generate ECO script to optimize on timing and electrical violation reduction
0-5 years of experience
- Buffer design (physical layout design) specialized IO cells
- Team member of IC library group-updated and maintained library of IO cells
- Created pad cell and corner cell designs
0-5 years of experience
Performed physical design and verification of field programmable gate array custom digital integrated circuit chips.
- Coordinated all physical layout activities, including full chip and block level IV mask designs
- Usage of proprietary tool for layout, verification testing, and design rule check
- Received in-house training in Cadence layout tool
0-5 years of experience
Responsible for performing synthesis on an 8M gate 45nm design using
Synopsys’ dc_shell tool.
- Responsible for floorplanning of a 4M gate, 45nm mixed signal design
- Responsible for place and route of 3 1M gate and 3 500K 45nm blocks
- Duties included floor planning, place and route, clock tree synthesis, extraction,
0-5 years of experience
- Implemented full Place & Route for a block with a physical design challenges: 56 SRAM, 36 Register File, 800K stdcell instances, 10 clock domains running at frequency ranging from 675Mhz to 33Mhz with 9 Metal layers, operating at 1.05 voltage.
- Explored multiple floorplan, EBB arrangement, placement options & ICC techniques (i.e. setting special routing rules, route guide, route blockages, pre-route of critical nets, including search and repair loop to improve large number of shorts in design) to solve congestion/routability.
- Extensive use of timing closer techniques like incremental optimization, path groups, placement blockages, logic bounds, keepout margin and cell density control option. Constraint analysis and review for cleaner SDC and improving the interface timing by adjusting the input/output delays.
- Worked with Full Chip Timing Owner in identifying optimal solution for hold buffer minimization (for cross clock hold paths exposed by design) through clock tree tuning/optimization, derating adjustment and flow step alteration for setup/hold. This resulted in over 10K buffer saving.
- Power reduction with limited cell swap and no routing change.
- Performed timing (setup/hold/SI/cap/tran) and functional ecos and delivered necessary data for full chip PV and physical integration roll-up.
- Built partition level timing model using prime time and supported to generate timing ECO.
- Performed Formal Verification on the block.
- Owned DFM closure on the block for tapein by resolving all DRC, NAC, DEN and LVS issues. This required manual fixing as well as TCL automation for better DFM TPT. Owned partition level checklist closure for all checks/signoff necessary to make tapein ready.
0-5 years of experience
Roles and responsibilities:
- Did Synthesis and Static Timing Analysis
- Did Scan insertion and Pattern Generation for ATE
- Used clock gating feature to achieve the dynamic power target.
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Physical Design Engineer
Last edited by: Gabriela Barcenas, CONTENT STRATEGIST -
Gabriela Barcenas
CONTENT STRATEGISTGabriela is a Certified Professional Resume Writer (CPRW) and career adviser. With 10 years of digital media experience and five years of resume writing expertise, her publication history includes fashion, education, travel, social justice, equitable design and career advice.
